1. Technical Field
The present disclosure relates to a circuit for translating a voltage level. Such a circuit may be used in input/output interfaces of an integrated circuit. Indeed, in integrated circuits, the data may have very low voltage levels, which may need to be increased for the processing by the circuits external to the integrated circuits, which operate under high voltages.
2. Description of the Related Art
FIG. 1 shows a conventional voltage-level translator circuit 1.
Circuit 1 comprises an input data-IN receiving input data from an integrated circuit. The data are digital data, with their two states respectively corresponding to a zero voltage (ground GND) and to a positive voltage VDD. Input data-IN is connected to the gate of an NMOS transistor M0. The source of transistor M0 is connected to a node M connected to ground GND. The drain of transistor M0 is connected to a node A.
Circuit 1 also comprises a PMOS transistor M′0 having its drain connected to node A. The source of transistor M′0 is connected to a node N connected to a supply terminal having a voltage V+ higher than voltage VDD. The gate of transistor M′0 is connected to a node B.
Circuit 1 also comprises an input data-IN which receives inversion data data that are inversions of the input data. Input data-IN drives the gate of an NMOS transistor M1. The source of transistor M1 is connected to node M. The drain of transistor M1 is connected to node B.
Circuit 1 also comprises a PMOS transistor M′1 having its drain connected to node B. The source of transistor M′1 is connected to node N. The gate of transistor M′1 is connected to node A.
Node B is connected to an output DATA-OUT which issues output data corresponding to the input data. Output data have a high level, also called high state or state or level 1, corresponding to voltage V+ and a low level, also called low state or state or level 0, corresponding to zero. Node A is connected to an output DATA-OUT which provides the inverse of output data.
The operation of the circuit of FIG. 1 will be discussed in relation with FIGS. 2a to 2f which schematically illustrate various timing diagrams of variables involved in circuit 1.
At time t=0, the input data (FIG. 2a) are at a low state and the voltage at input data-IN is equal to zero. Transistor M0 is off and, neglecting a leakage current, the drain-source current IDS(M0) running through transistor M0 (FIG. 2d) is zero. At time t=0, data data (FIG. 2b) are at a high state and the voltage at input data-IN is equal to voltage VDD. Transistor M1 is then on and voltage VB at node B is (substantially) zero (FIG. 2e). The voltage at node B being zero, transistor M′0 is on and voltage VA at node A (FIG. 2c) is equal to V+. The gate of transistor M′1 being at voltage V+, transistor M′1 is off and the drain-source current IDS(M1) running through transistor M1 (FIG. 2f) is zero (neglecting its leakage current).
At time t=t1, the input data switch from the low state to the high state and data data switch from the high state to the low state. Transistor M0 turns on and the voltage at node A will decrease. This decrease is not instantaneous and the voltage at node A reaches 0 at time t′1. Difference t′1-t1 corresponds to the switching time and, between times t1 and t′1, current IDS(M0) increases, crosses a threshold, then decreases back to recover value 0 at time t′1. As concerns node B, transistor M1 turns off at time t1 and the voltage at node B rises from the time when transistor M′1 starts conducting. At the end of the transition, at time t′1, node A is 0, node B is at V+, transistors M0 and M′1 are on, and transistors M1 and M′0 are off.
At time t2, the input data switch from state 1 to state 0 and data data switch from state 0 to state 1. Transistor M0 turns off and transistor M1 turns on. The voltage at node A increases to reach value V+ at time t′2 and the voltage at node B decreases to reach value 0 at time t′2. During the transition, the current in transistors M1 and M′1 first increases, then decreases, while the voltage at node B decreases and the voltage at node A increases. After time t′2, transistors M1 and M′0 are on, and transistors M0 and M′1 are off.
The circuit of FIG. 1 has disadvantages. The current tendency in the art is to have increasingly small voltages VDD, which results in increasing switching times. Thus, when voltage VDD comes close to the threshold of transistors M0 and M1, said transistors operate with a low gate/source voltage, which limits their saturation current and the state of nodes A and B cannot change fast.
A solution to decrease switching times would be to increase the saturation current of transistors M0 and M1 by increasing the size of transistors M0 and M1. However, in this case, the required silicon surface area risks being incompatible with the desired application. Further, this solution would increase the stray capacitance and the leakage current of transistors M0 and M1.